1. Field of the Invention
The present invention relates in general to a frequency detector, and in particular, to a component of a semiconductor integrated circuit that detects abnormalities in the frequency of the semiconductor's system clock.
2. Description of the Related Art
To synchronize the timing of microcontrollers or other peripheral devices in a microprocessor, a pulse or signal waveform generator is typically used to generate precisely timed voltage pulses at a fixed frequency and amplitude. Industry standard microprocessors can have clock inputs driven by a crystal, an LC tuned circuit, an external clock source or a system clock incorporated in the microcontroller. Often, the system clock in the microcontroller is connected to external components, such as a quartz oscillator and a capacitor, via external terminals of the microcontroller. The frequency of the system clock signal is determined by the quartz oscillator.
Maintaining precise control of the operating environment with respect to the clock circuitry is extremely important. For example, should the quartz oscillator or any capacitor connected to the external terminals of the microcontroller be exposed to moisture or foreign material, additional capacitance could cause variations to occur in the oscillatory frequency of the system clock. This in turn could result in device timing instability and microcontroller time shifting.
Deviations in the timing of digital circuitry beyond allowable tolerances can be a contributing factor in the misapplication of a high or low potential signal to a particular digital device. Should a low potential be asserted to a device when a high potential is expected, device malfunction could result. Fluctuations in oscillation frequency often preclude predetermined device control procedures and programming. For the above reasons, microcontrollers manufactured today require variant oscillation detecting circuitry designed to detect unexpected fluctuations in the oscillation frequency of the system clock.
FIG. 1 is an illustration of a frequency detector typically used in microcontroller circuitry. The microcontroller 110 is equipped with an oscillation circuit 111 for generating a system or operational clock signal CLK0. The oscillation circuit 111 includes a resistor 111a and two inverters 111b and 111c. The resistor 111a and the inverter 111b are connected in parallel. The oscillation circuit 111 is connected to external terminals T1 and T2 of the microcontroller 110. The external terminals T1 and T2 are grounded via capacitors C1 and C2, respectively. A quartz oscillator XTL0 is provided between the terminals T1 and T2.
The oscillation frequency of the system clock signal CLK0 is determined by the resistance and capacitance of the oscillation circuit 111 and the quartz oscillator XTL0. The system clock signal CLK0 is supplied from the inverter 111c of the oscillation circuit 111 to an edge detector 114 via an internal circuit (not shown) and a frequency divider 113. The frequency divider 113 divides the frequency of the system clock signal CLK0 with a predetermined dividing ratio to generate a pulse signal CL1, as shown in the timing chart of FIG. 2. The pulse signal CL1 is supplied to the edge detector 114. The edge detector 114 detects the rising edge of the pulse signal CL1 and outputs a pulse signal CLK1 high for predetermined period starting with the rise of pulse signal CL1.
The microcontroller 110 further includes a reference oscillator 116, a frequency divider 117 and a counter 115. The reference oscillator 116 is a ring-type oscillator circuit and supplies the frequency divider 117 with a reference clock signal CL3 at a predetermined frequency. The frequency divider 117 divides the frequency of the reference clock signal CL3 by a predetermined ratio to generate a reference clock signal CLK2, as shown in FIG. 2.
The counter 115 counts the number of reference clock signals CLK2 and uses the pulse signal CLK1 as a reset or clear signal to detect variations in the frequency of the system clock signal CLK0. Specifically, the counter 115 counts the number of pulses of the reference clock signal CLK2, by reference to the leading edge of the signal CLK2. The counter 115 also clears a current count value in response to a leading edge of the pulse signal CLK1 (i.e., sets the counting value to zero). In response to a trailing edge of the pulse signal CLK1, the counter 115 drops the clear signal to restart the counting operations. When the count value of the clock signal CLK2 reaches a predetermined value, the counter 115 outputs a high-level detection signal E1 indicating that the oscillation frequency of the signal CLK0 at an unexpected level. If the frequency of the system clock signal CLK0 is reduced, for example, the period of the pulse signal CLK1 increases, and the timing for clearing the counter 115 is delayed. The count value of the reference clock signal CLK2, in this situation, is more likely to reach the specified value. Counter 115 generates a high potential detection signal E1 to initialize the internal circuits and external peripheral devices. Signal E1, output high from the counter 115, initializes each of these devices.
When the oscillation frequency of the system clock signal CLK0 is within normal operating limits, the period of the pulse signal CLK1 will also be within normal operating limits. The counter 115 consequently can receive the pulse signal CLK1 and clear the count value before a target value signal CLK2 reaches its target value. Consequently, the counter 115 will not output detection signal E1 high as long as the oscillation frequency of the system clock signal CLK0 is within expected limits.
Because the system clock CLK0 is generated by oscillation circuit 111, and because the reference clock signal CL3 is generated by the reference oscillator 116, the system clock signal CLK0 in conventional frequency detectors is most often not synchronized with the reference clock signal CL3. In conventional detectors, should the falling edge of the pulse signal CLK1 coincide with the rising edge of the reference clock signal CLK2, the counter 115 would receive two signals CLK1 and CLK2. When this happens, the counter 115 often generates "counter noise" on the signal E1, as shown in FIG. 2, even though the count value has not reached a target or specified value. Because most detectors regard this noise as a high-level detection signal E1, the noise often causes time shifting to occur with the microcontroller 110.
Moreover, should the voltage supply to the microcontroller 110 drop for any reason, clock signal CLK0 may be obscured or even omitted in conventional detectors, due to an externally generated noise. Without the pulse signal CLK0, the period during which pulse signal CL1 is high increases, further delaying the next high pulse of signal CLK1. With a delay in the pulse signal CLK1, the reference clock signal CLK2 will cycle for a predetermined period, causing the counter 115 to output detection signal E1 high. Unintended output of detection signal E1 high can result in time shifting by the microcontroller 110.
Occasionally, microcontroller 110 comes equipped with a different type of frequency detector that can detect an increase in the oscillation frequency of the system clock signal CLK0. This type detector is substantially the same as described above and illustrated in FIG. 1, except that the detector uses a counter, much like counter 115, to count the pulses of the system clock signal CLK0. This type of counter tracks the pulses of the system clock signal CLK0, and clears the count value at a predetermined time interval. When the count value of the system clock signal CLK0 reaches a particular value, the counter outputs detection signal E1 high to indicate unacceptable deviation in the frequency of the system clock signal CLK0.
The higher oscillation frequencies of system clock signal CLK0 causes its period to decrease and count value to increase before it can be reset or cleared. The clock's count value is typically cleared before reaching the particular value, as long as the counter receives the system clock signal CLK0 at the proper frequency.
Microcontrollers and their peripheral devices typically control products having various timing requirements. To meet these requirements, the frequency of the system clock signal should be adjusted whenever necessary to the proper frequency. Moreover, variations in the operating frequency are often necessary.
For example, in order to reduce power consumption for some electronic devices, the frequency of the system clock signal will often change. When an internal circuit is in a standby state, the frequency of the system clock signal may be reduced to decrease an operation speed of the internal circuit. When fully powered, the internal circuit often requires an increase in the frequency of the system clock in order to effect high speed circuit operation. Microcontroller power consumption, therefore, may be reduced by decreasing the internal circuit's operational speed to that of a standby state.
One method commonly used to change system frequency is to selectively use two external quartz oscillators. A second commonly used method is to change the frequency of a clock signal input from an external circuit.
Unfortunately, conventional frequency detectors are often unable to distinguish unexpected variations in a system clock signal from normal variations. This often happens because the system clock count values and the clock reset period are often constant values and do not account for changes in the oscillation frequency of the clock.